This application claims the benefit of Application No. 47184/2000, filed in Korea on Aug. 16, 2000, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device having an elevated source/drain scheme.
2. Description of the Related Art
Recently, as the degree of integration of a semiconductor device increases, the length of a gate becomes smaller. Due to this, a number of problems referred to as a short channel effect occur, in particular, a punch through phenomenon is a serious problem. Thus, people become more concerned with a method for increasing the degree of integration of the device and at the same time suppressing the generation of a punch through phenomenon.
To satisfy this concern, a semiconductor device having an elevated source/drain scheme is devised.
A normal semiconductor device according to the conventional art includes a gate electrode formed on the top surface of a semiconductor substrate, source/drain junctions formed in the semiconductor substrate at both sides of the gate electrode, and a channel region between the source junction and the drain junction. That is, the top surface of the source/drain junctions is positioned on the same plane with the top surface of the channel region. In a semiconductor device having an elevated source/drain scheme, however, a channel is formed around the surface of the semiconductor substrate below the gate electrode as in the conventional art, while a source/drain is formed by selectively growing an epitaxial silicon layer on the top surface of the semiconductor substrate, thus making the top surface of the source/drain higher than the top surface of the channel.
The structure of the semiconductor device having an elevated source/drain scheme will now be described with reference to FIG. 1.
At a predetermined portion of a semiconductor substrate 10, a field oxide film 20 is formed in order to define an active region. That is, a portion at which the field oxide film 20 is not formed is an active region. On the top surface of the semiconductor substrate 10, a gate oxide film 11 is formed, and on the top surface of the gate oxide film 11, a gate electrode 12 is formed. In addition, a side wall spacer 13 is formed at the sides of the gate oxide film 12. In addition, a source extrusion portion 14a and a drain extrusion portion 15a are formed on the top surface of the semiconductor substrate at both sides of the gate electrode 12. A source junction 14b is formed within the semiconductor substrate 10 below the source extrusion portion 14a, and a drain junction 15b is formed within the semiconductor substrate 10 below the drain extrusion portion 15a. A channel 16 is formed within the semiconductor substrate 10 between the source junction 14b and the drain junction 15b. 
In other words, in the semiconductor device of FIG. 1, a source 14 is a combination of the source extrusion portion 14a and the source junction 14b, and a drain 15 is a combination of the drain extrusion portion 15a and the drain junction 15b. By making such a scheme, it is advantageous in that the depth of the source junction 14b and drain junction 15b becomes much smaller than that of the conventional semiconductor device.
However, in the semiconductor device having an elevated source/drain scheme according to the conventional art, there occurs a problem in the method therefor. That is, the source extrusion portion 14a and the drain extrusion portion 15a are generally formed by the epitaxial deposition method. However, the source extrusion portion 14a and the drain extrusion portion 15a formed by the epitaxial deposition method each have a facet 17 at their peripheral portion. In other words, the peripheral portion is formed thinner than the central portion is. Due to this, when ions are implanted so as to form the source/drain junctions 14b and 15b, the impurity ions are deeply implanted below the facet 17. That is, a deep junction is formed within the semiconductor substrate around the gate electrode 12, thus making it ineffective to prevent a punch through.
Accordingly, the present invention provides a method for fabricating a semiconductor device having an elevated source/drain scheme without using the epitaxial growing method.
In addition, the present invention provides a method for fabricating a semiconductor device having an elevated source/drain scheme using a dual photoresist process of ArF photoresist and KrF photoresist in such a manner that a conventional process is not much changed.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve the above objects, there is provided a method for fabricating a semiconductor device having an elevated source/drain scheme according to the present invention which includes the steps of: forming a first photoresist film on a top surface of a semiconductor substrate; forming a second photoresist film on the first photoresist film; forming a second photoresist film pattern so that a portion corresponding to a field region has a first opening and a region in which a gate electrode is to be formed has a second opening by exposing the second photoresist film to a first light, thereby developing the second photoresist film; forming a first photoresist film pattern so that a portion corresponding to the field region has a third opening by exposing the first photoresist film to a second light, thereby developing the first photoresist film; forming a first trench at the first opening position and a second trench at the second opening position on the semiconductor substrate by etching the semiconductor substrate using the first photoresist film pattern and the second photoresist film pattern as a mask; filling the first trench and second trench with an oxide film; removing the oxide film in the second trench; forming a gate oxide film on the inner walls of the first and second trenches and on the top surface of the semiconductor substrate; forming a gate electrode on the top surface of the second trench by forming a conductive layer on a top surface of the gate oxide film and patterning the gate oxide film; and forming a source junction and a drain junction by implanting impurity ions in the semiconductor substrate at both sides of the gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.